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1CY2308
CY2308
3.3V Zero Delay Buffer
Features
* Zero input-output propagation delay, adjustable by capacitive load on FBK input * Multiple configurations, see "Available CY2308 Configurations" table * Multiple low-skew outputs -- Output-output skew less than 200 ps -- Device-device skew less than 700 ps -- Two banks of four outputs, three-stateable by two select inputs * 10-MHz to 133-MHz operating range * Low jitter, less than 200 ps cycle-cycle (-1, -1H, -4, -5H) * Space-saving 16-pin 150-mil SOIC package or 16-pin TSSOP * 3.3V operation * Industrial Temperature available The CY2308 has two banks of four outputs each, which can be controlled by the Select inputs as shown in the table "Select Input Decoding." If all output clocks are not required, Bank B can be three-stated. The select inputs also allow the input clock to be directly applied to the output for chip and system testing purposes. The CY2308 PLL enters a power-down state when there are no rising edges on the REF input. In this mode, all outputs are three-stated and the PLL is turned off, resulting in less than 50 A of current draw. The PLL shuts down in two additional cases as shown in the "Select Input Decoding" table. Multiple CY2308 devices can accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is guaranteed to be less than 700 ps. The CY2308 is available in five different configurations, as shown in the "Available CY2308 Configurations" table on page 2. The CY2308-1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. The CY2308-1H is the high-drive version of the -1, and rise and fall times on this device are much faster. The CY2308-2 allows the user to obtain 2X and 1X frequencies on each output bank. The exact configuration and output frequencies depends on which output drives the feedback pin. The CY2308-3 allows the user to obtain 4X and 2X frequencies on the outputs. The CY2308-4 enables the user to obtain 2X clocks on all outputs. Thus, the part is extremely versatile, and can be used in a variety of applications. The CY2308-5H is a high-drive version with REF/2 on both banks.
Functional Description
The CY2308 is a 3.3V Zero Delay Buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications. The part has an on-chip PLL which locks to an input clock presented on the REF pin. The PLL feedback is required to be driven into the FBK pin, and can be obtained from one of the outputs. The input-to-output skew is guaranteed to be less than 350 ps, and output-to-output skew is guaranteed to be less than 200 ps.
Block Diagram
/2
REF
Pin Configuration
PLL
MUX
FBK CLKA1 CLKA2 CLKA3 CLKA4 REF CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2
/2
Extra Divider (-3, -4) Extra Divider (-5H)
SOIC Top View
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
S2 S1
FBK CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1
Select Input Decoding
/2
CLKB1 CLKB2 CLKB3
Extra Divider (-2, -3)
CLKB4
Cypress Semiconductor Corporation Document #: 38-07146 Rev. *C
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Revised June 16, 2004
CY2308
Pin Description
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 REF
[1]
Signal CLKA1[2] CLKA2 VDD GND CLKB1[2] CLKB2 S2[3] S1
[3] [2] [2] [2]
Description Input reference frequency, 5V tolerant input Clock output, Bank A Clock output, Bank A 3.3V supply Ground Clock output, Bank B Clock output, Bank B Select input, bit 2 Select input, bit 1 Clock output, Bank B Clock output, Bank B Ground 3.3V supply Clock output, Bank A Clock output, Bank A PLL feedback input
CLKB3 GND VDD
CLKB4[2]
CLKA3[2] CLKA4[2] FBK
Select Input Decoding
S2 0 0 1 1 S1 0 1 0 1 CLOCK A1-A4 Three-State Driven Driven
[4]
CLOCK B1-B4 Three-State Three-State Driven[4] Driven
Output Source PLL PLL Reference PLL
PLL Shutdown Y N Y N
Driven
Available CY2308 Configurations
Device CY2308-1 CY2308-1H CY2308-2 CY2308-2 CY2308-3 CY2308-3 CY2308-4 CY2308-5H Feedback From Bank A or Bank B Bank A or Bank B Bank A Bank B Bank A Bank B Bank A or Bank B Bank A or Bank B Bank A Frequency Reference Reference Reference 2 X Reference 2 X Reference 4 X Reference 2 X Reference Reference /2 Bank B Frequency Reference Reference Reference/2 Reference Reference or Reference[5] 2 X Reference 2 X Reference Reference /2
Notes: 1. Weak pull-down. 2. Weak pull-down on all outputs. 3. Weak pull-ups on these inputs. 4. Outputs inverted on 2308-2 and 2308-3 in bypass mode, S2 = 1 and S1 = 0. 5. Output phase is indeterminant (0 or 180 from input clock). If phase integrity is required, use the CY2308-2.
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CY2308
Zero Delay and Skew Control
REF. Input to CLKA/CLKB Delay v/s Difference in Loading between FBK pin and CLKA/CLKB Pins
To close the feedback loop of the CY2308, the FBK pin can be driven from any of the eight available output pins. The output driving the FBK pin will be driving a total load of 7 pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the inputoutput delay. This is shown in the graph above. For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. If input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs. For zero output-output skew, be sure to load outputs equally. For further information on using CY2308, refer to the application note "CY2308: Zero Delay Buffer."
Maximum Ratings
Supply Voltage to Ground Potential ...............-0.5V to +7.0V DC Input Voltage (Except Ref) .............. -0.5V to VDD + 0.5V DC Input Voltage REF ........................................... -0.5 to 7V Storage Temperature.................................. -65C to +150C Junction Temperature...................................................150C Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................. >2000V
Operating Conditions for CY2308SC-XX Commercial Temperature Devices
Parameter VDD TA CL CIN tPU Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz Input Capacitance[6] 0.05 Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Description Min. 3.0 0 Max. 3.6 70 30 15 7 50 Unit V C pF pF pF ms
Note: 6. Applies to both Ref Clock and FBK.
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CY2308
Electrical Characteristics for CY2308SC-XX Commercial Temperature Devices
Parameter VIL VIH IIL IIH VOL VOH IDD (PD mode) IDD Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage
[7]
Test Conditions
Min. 2.0
Max. 0.8
Unit V V A A V V
VIN = 0V VIN = VDD IOL = 8 mA (-1, -2, -3, -4) IOL = 12 mA (-1H, -5H) IOH = -8 mA (-1, -2, -3, -4) IOH = -12 mA (-1H, -5H) Unloaded outputs, 100-MHz REF, Select inputs at VDD or GND Unloaded outputs, 66-MHz REF (-1, -2, -3, -4) Unloaded outputs, 33-MHz REF (-1, -2, -3, -4) 2.4
50.0 100.0 0.4
Output HIGH Voltage[7]
Power Down Supply Current REF = 0 MHz Supply Current
12.0 45.0 70.0 (-1H,-5H) 32.0 18.0
A mA mA mA mA
Note: 7. Parameter is guaranteed by design and characterization. Not 100% tested in production.
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CY2308
Switching Characteristics for CY2308SC-XX Commercial Temperature Devices [8]
Parameter t1 t1 t1 Name Output Frequency Output Frequency Output Frequency Duty Cycle[7] = t2 / t1 (-1, -2, -3, -4, -1H, -5H) Duty Cycle[7] = t2 / t1 (-1, -2, -3, -4, -1H, -5H) t3 t3 t3 t4 t4 t4 t5 Rise Time[7] (-1, -2, -3, -4) Rise Time[7] (-1, -2, -3, -4) Rise Time[7] (-1H, -5H) Fall Time[7] (-1, -2, -3, -4) Fall Time[7] (-1, -2, -3, -4) Fall Time[7] (-1H, -5H) Output to Output Skew on same Bank (-1, -2, -3, -4)[7] Output to Output Skew (-1H, -5H) Test Conditions 30-pF load, All devices 20-pF load, -1H, -5H devices[9] 15-pF load, -1, -2, -3, -4 devices Measured at 1.4V, FOUT = 66.66 MHz 30-pF load Measured at 1.4V, FOUT <50.0 MHz 15-pF load Measured between 0.8V and 2.0V, 30-pF load Measured between 0.8V and 2.0V, 15-pF load Measured between 0.8V and 2.0V, 30-pF load Measured between 0.8V and 2.0V, 30-pF load Measured between 0.8V and 2.0V, 15-pF load Measured between 0.8V and 2.0V, 30-pF load All outputs equally loaded Min. 10 10 10 40.0 45.0 50.0 50.0 Typ. Max. 100 133.3 133.3 60.0 55.0 2.20 1.50 1.50 2.20 1.50 1.25 200 Unit MHz MHz MHz % % ns ns ns ns ns ns ps
All outputs equally loaded
200 200 400 0 0 1 200 200 100 400 400 1.0 250 700
ps ps ps ps ps V/ns ps ps ps ps ps ms
Output Bank A to Output All outputs equally loaded Bank B Skew (-1, -4, -5H) Output Bank A to Output Bank B Skew (-2, -3) t6 t7 t8 tJ All outputs equally loaded
Delay, REF Rising Edge to Measured at VDD/2 FBK Rising Edge[7] Device to Device Skew[7] Output Slew Rate[7] Cycle to Cycle Jitter[7] (-1, -1H, -4, -5H) Measured at VDD/2 on the FBK pins of devices Measured between 0.8V and 2.0V on -1H, -5H device using Test Circuit #2 Measured at 66.67 MHz, loaded outputs, 15-pF load Measured at 66.67 MHz, loaded outputs, 30-pF load Measured at 133.3 MHz, loaded outputs, 15-pF load
tJ
Cycle to Cycle Jitter[7] (-2, -3)
Measured at 66.67 MHz, loaded outputs 30-pF load Measured at 66.67 MHz, loaded outputs 15-pF load
tLOCK
PLL Lock Time[7]
Stable power supply, valid clocks presented on REF and FBK pins
Notes: 8. All parameters are specified with loaded outputs. 9. CY2308-5H has maximum input frequency of 133.33 MHz and maximum output of 66.67 MHz.
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CY2308
Operating Conditions for CY2308SI-XX Industrial Temperature Devices
Parameter VDD TA CL CIN tPU Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz Input Capacitance[6] Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05 Description Min. 3.0 -40 Max. 3.6 85 30 15 7 50 Unit V C pF pF pF ms
Electrical Characteristics for CY2308SI-XX Industrial Temperature Devices
Parameter VIL VIH IIL IIH VOL VOH IDD (PD mode) IDD Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage[7] Output HIGH Voltage[7] Power Down Supply Current Supply Current VIN = 0V VIN = VDD IOL = 8 mA (-1, -2, -3, -4) IOL = 12 mA (-1H, -5H) IOH = -8 mA (-1, -2, -3, -4) IOH = -12 mA (-1H, -5H) REF = 0 MHz Unloaded outputs, 100 MHz, Select inputs at VDD or GND Unloaded outputs, 66-MHz REF (-1, -2, -3, -4) Unloaded outputs, 66-MHz REF (-1, -2, -3, -4) 2.4 25.0 45.0 70(-1H,-5H) 35.0 20.0 2.0 50.0 100.0 0.4 Test Conditions Min. Max. 0.8 Unit V V A A V V A mA mA mA mA
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CY2308
Switching Characteristics for CY2308SI-XX Industrial Temperature Devices [8]
Parameter t1 t1 t1 Name Output Frequency Output Frequency Output Frequency Duty Cycle[7] = t2 / t1 (-1, -2, -3, -4, -1H, -5H) Duty Cycle[7] = t2 / t1 (-1, -2, -3, -4, -1H, -5H) t3 t3 t3 t4 t4 t4 t5 Rise Time[7] (-1, -2, -3, -4) Rise Time[7] (-1, -2, -3, -4) Rise Time[7] (-1H, -5H) Fall Time[7] (-1, -2, -3, -4) Fall Time[7] (-1, -2, -3, -4) Fall Time[7] (-1H, -5H) Test Conditions 30-pF load, All devices 20-pF load, -1H, -5H devices[9] 15-pF load, -1, -2, -3, -4 devices Measured at 1.4V, FOUT = 66.66 MHz 30-pF load Measured at 1.4V, FOUT <50.0 MHz 15-pF load Measured between 0.8V and 2.0V, 30-pF load Measured between 0.8V and 2.0V, 15-pF load Measured between 0.8V and 2.0V, 30-pF load Measured between 0.8V and 2.0V, 30-pF load Measured between 0.8V and 2.0V, 15-pF load Measured between 0.8V and 2.0V, 30-pF load Min. 10 10 10 40.0 45.0 50.0 50.0 Typ. Max. 100 133.3 133.3 60.0 55.0 2.50 1.50 1.50 2.50 1.50 1.25 200 200 200 400 0 0 1 200 200 100 400 400 1.0 250 700 Unit MHz MHz MHz % % ns ns ns ns ns ns ps ps ps ps ps ps V/ns ps ps ps ps ps ms
Output to Output Skew on All outputs equally loaded same Bank (-1, -2, -3, -4)[7] Output to Output Skew (-1H, -5H) Output Bank A to Output Bank B Skew (-1, -4, -5H) Output Bank A to Output Bank B Skew (-2, -3) All outputs equally loaded All outputs equally loaded All outputs equally loaded Measured at VDD/2 Measured at VDD/2 on the FBK pins of devices Measured between 0.8V and 2.0V on -1H, -5H device using Test Circuit # 2 Measured at 66.67 MHz, loaded outputs, 15-pF load Measured at 66.67 MHz, loaded outputs, 30-pF load Measured at 133.3 MHz, loaded outputs, 15 pF load
t6 t7 t8 tJ
Delay, REF Rising Edge to FBK Rising Edge[7] Device to Device Skew[7] Output Slew Rate[7] Cycle to Cycle Jitter[7] (-1, -1H, -4, -5H)
tJ
Cycle to Cycle Jitter[7] (-2, -3)
Measured at 66.67 MHz, loaded outputs 30-pF load Measured at 66.67 MHz, loaded outputs 15-pF load
tLOCK
PLL Lock Time[7]
Stable power supply, valid clocks presented on REF and FBK pins
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CY2308
Switching Waveforms
Duty Cycle Timing
t1 t2 1.4V 1.4V 1.4V
All Outputs Rise/Fall Time
2.0V 0.8V t3 2.0V 0.8V t4 3.3V 0V
OUTPUT
Output-Output Skew
OUTPUT
1.4V
OUTPUT t5
1.4V
Input-Output Propagation Delay
INPUT
VDD/2
FBK t6
VDD/2
Device-Device Skew
FBK, Device 1
VDD/2
FBK, Device 2 t7
VDD/2
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CY2308
Typical Duty Cycle[10] and IDD Trends[11] for CY2308-1,2,3,4
Duty Cycle Vs VDD (for 30 pF Loads over Frequency - 3.3V, 25C)
60 58 56 Duty Cycle (% )
Duty Cycle Vs VDD (for 15 pF Loads over Frequency - 3.3V, 25C)
60 58 56 Duty Cycle (% ) 54 52 50 48 46 44 42 40 33 MHz 66 MHz 100 MH z 133 MH z
54 52 50 48 46 44 42 40 3 3.1 3.2 3.3 VDD (V) 3.4 3.5 3.6 33 MHz 66 MHz 100 MHz
3
3.1
3.2
3.3 VDD (V)
3.4
3.5
3.6
Duty Cycle Vs Frequency (for 30 pF Loads over Temperature - 3.3V)
60 58 56 Duty Cycle (%)
Duty Cycle Vs Frequency (for 15 pF Loads over Temperature - 3.3V)
60 58 56
0C 25C 70C 85C -40C
52 50 48 46 44 42 40 20 40 60 80 Frequency (MHz) 100 120 140
Duty Cycle (%)
54
54 52 50 48 46 44 42 40 20 40 60 80 Frequency (MHz) 100 120 140
-40C 0C 25C 70C 85C
IDD vs Number of Loaded Outputs (for 30 pF Loads over Frequency - 3.3V, 25C)
140 120 100 80 60 40 20 0 0 2 4 6 8 # o f Lo ad ed Out p ut s
33 M Hz 66 M Hz 1 00 M Hz
IDD vs Number of Loaded Outputs (for 15 pF Loads over Frequency - 3.3V, 25C)
140 120 100 80 60 40 20 0 0 2 4 # o f Lo a de d Ou t p ut s 6 8
33 M Hz 66 M Hz 1 00 M Hz
Notes: 10. Duty Cycle is taken from typical chip measured at 1.4V. 11. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current. (n = # of outputs; C = Capacitance load per output (F); V = Voltage Supply (V); f = frequency (Hz))
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CY2308
Typical Duty Cycle[10] and IDD Trends[11] for CY2308-1H, 5H
Duty Cycle Vs VDD (for 30 pF Loads over Frequency - 3.3V, 25C)
60 58 56 Duty Cycle (% )
Duty Cycle (% ) 60 58 56 54 52 50 48 46 44 42 40 33 M Hz 66 M Hz 100 MH z 133 MH z
Duty Cycle Vs VDD (for 15 pF Loads over Frequency - 3.3V, 25C)
54 52 50 48 46 44 42 40 3 3.1 3.2 3.3 VDD (V) 3.4 3.5 3.6 33 MHz 66 MHz 100 MHz
3
3.1
3.2
3.3 VDD (V)
3.4
3.5
3.6
Duty Cycle Vs Frequency (for 30 pF Loads over Temperature - 3.3V)
60 58 56 Duty Cycle (%)
60 60 58 58 56 56 54 54 52 52 50 50 48 48 46 46 44 44 42 42 40 40
Duty Cycle Vs Frequency Duty Cycle Vs VDD (for 15 pF Loads over Temperature - 25C) (for 15 pF Loads over Frequency - 3.3V,3.3V)
52 50 48 46 44 42 40 20 40 60 80 Frequency (MHz) 100 120 140
0C 25C 70C 85C
Duty Cycle (% ) Duty Cycle (%)
54
-40C
-40C 33 M Hz 0C
66 M Hz 25C 100 MH z 70C 133 MH z 85C
20 3
40 3.1
60 3.2
80 3.3 Frequency (MHz) VDD (V)
100 3.4
120 3.5
140 3.6
IDD vs Number of Loaded Outputs (for 30 pF Loads over Frequency - 3.3V, 25C)
140 120 100 80 60 40 20 0 0 2 4 6 8 33 MHz 66 MHz 100 MHz 140 120 100 80 60 40 20 0 0
IDD vs Number of Loaded Outputs (for 15 pF Loads over Frequency - 3.3V, 25C)
33 MHz 66 MHz 100 MHz
2
4
6
8
# o f Lo a de d Ou t put s
# o f Loa de d Out p ut s
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CY2308
Test Circuits
Test Circuit # 1 VDD 0.1 F OUTPUTS V DD 0.1 F GND GND 0.1 F CLK OUT C LOAD Test Circuit # 2 V DD 0.1 F OUTPUTS 1 K V DD GND GND 1 K
CLK out 10 pF
Test Circuit for all parameters except t8
Test Circuit for t8, Output slew rate on -1H, -5 device
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CY2308
Ordering Information
Ordering Code CY2308SC-1 CY2308SI-1 CY2308SC-1H CY2308SI-1H CY2308ZC-1H CY2308ZI-1H CY2308SC-2 CY2308SI-2 CY2308SC-3 CY2308SI-3 CY2308SC-4 CY2308SI-4 CY2308SC-5H CY2308SI-5H CY2308ZC-5H CY2308ZI-5H Lead Free CY2308SXC-1 CY2308SXI-1 CY2308SXC-1H CY2308SXI-1H CY2308ZXC-1H CY2308ZXI-1H CY2308SXC-2 CY2308SXI-2 CY2308SXC-3 CY2308SXI-3 CY2308SXC-4 CY2308SXI-4 CY2308SXC-5H CY2308SXI-5H CY2308ZXC-5H CY2308ZXI-5H S16 S16 S16 S16 Z16 Z16 S16 S16 S16 S16 S16 S16 S16 S16 Z16 Z16 16-pin 150-mil SOIC 16-pin 150-mil SOIC 16-pin 150-mil SOIC 16-pin 150-mil SOIC 16-pin 150-mil TSSOP 16-pin 150-mil TSSOP 16-pin 150-mil SOIC 16-pin 150-mil SOIC 16-pin 150-mil SOIC 16-pin 150-mil SOIC 16-pin 150-mil SOIC 16-pin 150-mil SOIC 16-pin 150-mil SOIC 16-pin 150-mil SOIC 16-pin 150-mil TSSOP 16-pin 150-mil TSSOP Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Package Name S16 S16 S16 S16 Z16 Z16 S16 S16 S16 S16 S16 S16 S16 S16 Z16 Z16 Package Type 16-pin 150-mil SOIC 16-pin 150-mil SOIC 16-pin 150-mil SOIC 16-pin 150-mil SOIC 16-pin 150-mil TSSOP 16-pin 150-mil TSSOP 16-pin 150-mil SOIC 16-pin 150-mil SOIC 16-pin 150-mil SOIC 16-pin 150-mil SOIC 16-pin 150-mil SOIC 16-pin 150-mil SOIC 16-pin 150-mil SOIC 16-pin 150-mil SOIC 16-pin 150-mil TSSOP 16-pin 150-mil TSSOP Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial
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CY2308
Package Drawings and Dimensions
16 Lead (150 Mil) SOIC
8 1
16-Lead (150-Mil) SOIC S16.15
PIN 1 ID
DIMENSIONS IN INCHES[MM] MIN. MAX. REFERENCE JEDEC MS-012
0.150[3.810] 0.157[3.987] 0.230[5.842] 0.244[6.197]
PACKAGE WEIGHT 0.15gms
PART # S16.15 STANDARD PKG. 9 16 SZ16.15 LEAD FREE PKG.
0.386[9.804] 0.393[9.982]
SEATING PLANE
0.010[0.254] 0.016[0.406]
X 45
0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.0138[0.350] 0.0192[0.487] 0.004[0.102] 0.0098[0.249]
0~8
0.016[0.406] 0.035[0.889]
0.0075[0.190] 0.0098[0.249]
51-85068-*B
16-lead TSSOP 4.40 MM Body Z16.173
PIN 1 ID
1
DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153
6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177]
PACKAGE WEIGHT 0.05 gms PART # Z16.173 STANDARD PKG. ZZ16.173 LEAD FREE PKG.
16
0.65[0.025] BSC.
0.19[0.007] 0.30[0.012]
1.10[0.043] MAX.
0.25[0.010] BSC GAUGE PLANE 0-8
0.076[0.003] 0.85[0.033] 0.95[0.037] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008]
4.90[0.193] 5.10[0.200]
51-85091-*A
All product and company names mentioned in this document may be the trademarks of their respective holders Document #: 38-07146 Rev. *C Page 13 of 14
(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY2308
.Document History Page
Document Title: CY2308 3.3V Zero Delay Buffer Document Number: 38-07146 REV. ** *A *B *C ECN NO. 110255 118722 121832 235854 Issue Date 12/17/01 10/31/02 12/14/02 See ECN Orig. of Change SZV RGL RBI RGL Added Note 1 in page 2. Power up requirements added to Operating Conditions Information Added Lead Free Devices Description of Change Change from Spec number: 38-00528 to 38-07146
Document #: 38-07146 Rev. *C
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